1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for forming a contact between diffusion layers and metal wirings on a semiconductor substrate and metal wirings extending from the contacts.
2. Description of the Related Art
With the recent trend toward higher degrees of integration of elements and finer circuit patterns on semiconductor devices, contacts for electrically connecting circuit elements and wirings on the semiconductor devices are also formed in finer patterns. This tendency causes the tolerances for any positional misalignments at a manufacturing process between contact regions of diffusion layers formed on semiconductor substrates and contact holes to become severely constrained. If the contact hole is unduly displaced from the contact region of the diffusion layer beyond the tolerances, the wirings are short-circuited to the semiconductor substrate, and hence the semiconductor device will not operate properly.
To avoid the above drawback, it has been the customary practice to introduce, by ion implantation, impurities of the same conductivity type as diffusion layers to which a contact is to be made, through the contact hole, thereby preventing wirings from being short-circuited to the semiconductor substrate.
FIGS. 1(a)-1(d) show successive steps of a conventional process (hereinafter referred to as a first prior art) to manufacture semiconductor devices. In the illustrated process, a positional misalignment occurs at a manufacturing process between a contact region of a diffusion layer and a contact hole.
First, as shown in FIG. 1(a), a field oxide film 22 is selectively formed on a p-type semiconductor substrate 21, and an n.sup.+ -type diffusion layer 23 is formed in an active region which is not covered with the field oxide film 22. Thereafter, the entire surface formed thus far is covered with an interlayer insulating film 24, and a contact hole is defined in the interlayer insulating film 24, thereby exposing the substrate surface through the contact hole.
Then, as shown in FIG. 1(b), an oxide film 29 is grown to a thickness in the range of from 10 to 30 nanometers (nm) on the entire surface of the substrate, following which phosphorus (P) is ion-implanted into a contact region under condition that energy is 50 keV and dosage is 1.times.10.sup.15 cm.sup.-2. Subsequently, the substrate is annealed at 800.degree. C. for about 10 minutes to activate the ion-implanted phosphorus, thereby forming a phosphorus-dispersed layer 26.
The oxide film 29 is provided to prevent channeling of the implanted ions, to prevent a silicon surface from being contaminated with metal impurities upon ion implantation, and to prevent phosphorus from being out-diffused when the substrate is annealed.
After the anneal, as shown in FIG. 1(c), the oxide film 29 is removed by etching, thereby exposing the substrate surface in the contact hole.
Then, as shown in FIG. 1(d), a barrier metal layer 25 and a metal wiring 28 are formed, thereby completing a semiconductor device. The barrier metal layer 25 may be in the form of a titanium (Ti) film, a titanium nitride (TIN) film, or a combination thereof.
Modifications of the aforesaid prior art, particularly with respect to the formation of a silicide in the contact hole, are disclosed in Japanese Patent Laid-open Nos. 3-29321, 2-114634, and 60-138962. Japanese Patent Laid-open No. 3-29321 discloses a process (hereinafter referred to as a second prior art), in which after ions are implanted into a contact region, a silicide forming material is deposited on the substrate surface and annealed to form a silicide in the contact hole, and thereafter a metal wiring is formed.
FIGS. 2(a)-2(d) show successive steps of an improved process (hereinafter referred to as a third prior art) for manufacturing semiconductor devices as disclosed in Japanese Patent Laid-open Nos. 2-114634 and 60-138962. In this process, a positional misalignment occurs at a manufacturing process between a contact region of a dispersion layers and contact holes.
First, as shown in FIG. 2(a), a field oxide film 32 is selectively formed on a p-type semiconductor substrate 31, and an n.sup.+ -type diffusion layer 33 is formed in active regions which is not covered with the field oxide film 32. Thereafter, the entire surface formed thus far is covered with an interlayer insulating film 34, and a contact hole is formed in the interlayer insulating film 34, thereby exposing the substrate surface through the contact hole.
Then, as shown in FIG. 2(b), a metal of a high melting point, such as molybdenum (Mo) or the like, is deposited on the entire surface formed thus far, thereby forming a high melting-point metal film 35 having a thickness of about 50 nm. Thereafter, an n-type impurity such as of arsenic (As) or the like is ion-implanted into the contact region under such condition that energy is 70 kev and dosage is 4.times.10.sup.15 cm.sup.-2, thereby forming an arsenic-diffused layer 36.
Thereafter, as shown in FIG. 2(c), the molybdenum on the surface of the silicon substrate in the contact hole is silicided by being heat-treated at 550.degree. C. for about 30 minutes, thus forming a silicide film 37. Thereafter, the high melting-point metal which has not been silicided is removed by etching.
Then, as shown in FIG. 2(d), a metal wiring 38 is formed on the surface formed thus far, thereby completing a semiconductor device.
In the first prior art process, since ions are implanted through the oxide film, oxygen (O) in the oxide film is also implanted, together with phosphorus, into the substrate, causing an increase in the contact resistance and a degradation in the reliability of the contact between the n.sup.+ -type diffusion layer and the metal wiring. Furthermore, the oxide film needs to be formed for implantation of ions and then to be removed, and the barrier metal layer also needs to be formed. Accordingly, the first prior art process has a drawback such that it is complex and is composed of many steps.
The second prior art process enables reduction of the process steps because ions are implanted into the contact region without the need for forming an oxide film. Since ions are introduced into the surface of the silicon substrate which is exposed, it is impossible to prevent metal impurities such as of Fe or the like discharged from an ion implantation apparatus from being introduced into the surface of the silicon substrate when the ions are implanted. The metal impurities thus introduced are trapped in the defects in the silicon substrate, lowering the performance thereof, causing an increased leakage. The second prior art process has such a problem that ions implanted into the surface of the silicon substrate tend to cause channeling, resulting in an increase of the contact resistance.
The third prior art process shown in FIGS. 2(a)-2(d) also does not require the formation and removal of an oxide film because impurities are ion-implanted into the contact region through the high melting-point metal film. However, when an unreacted part of the high melting-point metal is removed after annealing, the surface of the silicide in the contact hole is exposed to the atmosphere, thereby forming a thin native oxide film, with the result that there are variations in the contact resistance and lowering of reliability.
The above shortcomings can be alleviated by removing by etching, the insulating oxide film. However, an additional etching step is required, and the thickness of the silicide film in the contact hole is reduced in the etching step.